The present invention is directed to semiconductor devices and particularly to CMOS SOI or SOS devices having radiation hardened characteristics.
Silicon-on-Insulator (SOI) technology has received considerably attention recently for development of high-density, radiation-hardened integrated circuits. The technology offers good potential for achieving a combination of radiation hardness and circuit density levels not attainable by bulk complementary metal oxide semiconductor (CMOS) or dielectrically isolated bipolar implementations. Interest in the technology has also been amplified by the recent availability of improved-quality oxygen-implanted SOI wafers. In particular, the SIMOX (Separation by IMplanted OXygen) approach is being considered as a production-capable process for providing high-quality SOI wafers. The following reference generally describes this technology. S. S. Tsao, D. M. Fleetwood, H. T. Weaver, L. Pfeiffer, and G. K. Cellar, "Radiation-Tolerant Sidewall-Hardened SOI/MOS Transistors," IEEE Trans. Nucl. Sci., Vol. NS-34, p. 1692, Dec. 87. This invention describes a fairly simple approach to development of radiation-hardened CMOS/SOI devices.
In CMOS/SOI radiation hardening, recent emphasis has mostly been on sidewall isolation, and two isolation approaches have been reported, The isolated mesa approach (with sloped sidewall) is an extension of device isolation techniques employed in CMOS/SOS where a MOS device is formed on a silicon layer on top of a sapphire substrate. Hardening of the sidewall in this case is implemented by using an appropriate hardened gate dielectric on the sidewall. There are some drawbacks with this approach: the sidewall transistor has different characteristics than the top channel transistor. The sidewall channel also connects the top channel to the back channel, which is not desirable due to potential corner effects: at the corners, the channel sees both the sidewall gate dielectric and the buried oxide. Even if the sidewall gate dielectric is hardened, buried oxide could cause radiation-inducted leakage at the two corners. Finally, the wafer topography is non-planar in this approach, and unless an effective planarization process is employed, it would have a low yield in metal definition.
Planarized polysilicon-filled trench isolation is another technique that has been applied for sidewall hardening. The sidewall hardness problem exists for oxide-isolated NMOS transistors because the channel along the sidewall can invert due to charge buildup in the isolation oxide. By using a polysilicon-filled trench in place of oxide isolation, the charge buildup problem can be reduced. However, this approach requires both the growth of a hardened gate oxide on the sidewall and a fairly difficult trench-definition-and-filling process, and these two requirements are not necessarily compatible. An important advantage of CMOS/SOI (or SOS) is its relative simplicity in device structure as compared to bulk CMOS. The addition of a difficult trench isolation process would detract from this advantage.